RTL hardware design using VHDL : coding for efficiency, portability, and scalability / Pong P. Chu.
2006
TK7868.D5 C46 2006eb
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Details
Title
RTL hardware design using VHDL : coding for efficiency, portability, and scalability / Pong P. Chu.
Author
ISBN
047178639X (electronic bk.)
9780471786399 (electronic bk.)
0471786411 (electronic bk.)
9780471786412 (electronic bk.)
1280448105
9781280448102
9786610448104
6610448108
0471720925 (Cloth)
9780471720928
9780471786399 (electronic bk.)
0471786411 (electronic bk.)
9780471786412 (electronic bk.)
1280448105
9781280448102
9786610448104
6610448108
0471720925 (Cloth)
9780471720928
Imprint
Hoboken, N.J. : Wiley-Interscience, ©2006.
Language
English
Description
1 online resource (xxiii, 669 pages) : illustrations
Other Standard Identifiers
10.1002/0471786411 doi
Call Number
TK7868.D5 C46 2006eb
System Control No.
(OCoLC)69253176
Summary
The skills and guidance needed to master RTL hardware designThis book teaches readers how to systematically design efficient, portable, and scalable Register Transfer Level (RTL) digital circuits using the VHDL hardware description language and synthesis software.
Bibliography, etc. Note
Includes bibliographical references (pages 665-666) and index.
Formatted Contents Note
Introduction to digital system design
Overview of hardware description languages
Basic language constructs of VHDL
Concurrent signal assignment statements of VHDL
Sequential statements of VHDL
Synthesis of VHDL code
Combinational circuit design : practice
Sequential circuit design : principle
Sequential circuit design : practice
Finite state machine : principle and practice
Register transfer methodology : principle
Register transfer methodology : practice
Hierarchical design in VHDL
Parameterized design : principle
Parameterized design : practice
Clock and synchronization : principle and practice.
Overview of hardware description languages
Basic language constructs of VHDL
Concurrent signal assignment statements of VHDL
Sequential statements of VHDL
Synthesis of VHDL code
Combinational circuit design : practice
Sequential circuit design : principle
Sequential circuit design : practice
Finite state machine : principle and practice
Register transfer methodology : principle
Register transfer methodology : practice
Hierarchical design in VHDL
Parameterized design : principle
Parameterized design : practice
Clock and synchronization : principle and practice.
Digital File Characteristics
data file
Source of Description
Print version record.
Available in Other Form
Print version: Chu, Pong P., 1959- RTL hardware design using VHDL. Hoboken, N.J. : Wiley-Interscience, ©2006
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