VLSI test principles and architectures : design for testability / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
2006
TK7874.75 .V587 2006eb
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Details
Title
VLSI test principles and architectures : design for testability / edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
ISBN
9780080474793 (electronic bk.)
0080474799 (electronic bk.)
9780123705976 (hbk.)
0123705975 (hbk.)
0080474799 (electronic bk.)
9780123705976 (hbk.)
0123705975 (hbk.)
Published
Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, [2006]
Copyright
©2006
Language
English
Description
1 online resource (xxx, 777 pages) : illustrations
Call Number
TK7874.75 .V587 2006eb
System Control No.
(OCoLC)162573568
Summary
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
Bibliography, etc. Note
Includes bibliographical references and index.
Formatted Contents Note
Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez
Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker
Test generation / Michael S. Hsiao
Logic built-in self-test / Laung-Terng (L.-T.) Wang
Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba
Logic diagnosis / Shi-Yu Huang
Memory testing and built-in self-test / Cheng-Wen Wu
Memory diagnosis and built-in self-repair / Cheng-Wen Wu
Boundary scan and core-based testing / Kuen-Jong Lee
Analog and mixed-signal testing / Chauchin Su
Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang.
Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker
Test generation / Michael S. Hsiao
Logic built-in self-test / Laung-Terng (L.-T.) Wang
Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba
Logic diagnosis / Shi-Yu Huang
Memory testing and built-in self-test / Cheng-Wen Wu
Memory diagnosis and built-in self-repair / Cheng-Wen Wu
Boundary scan and core-based testing / Kuen-Jong Lee
Analog and mixed-signal testing / Chauchin Su
Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang.
Source of Description
Print version record.
Series
Morgan Kaufmann series in systems on silicon.
Available in Other Form
Print version: VLSI test principles and architectures. Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, ©2006
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